1. Field of the Invention
The present invention relates to a manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device, and more particularly, to a manufacturing method of a HV MOS transistor device for reducing leakage current.
2. Description of the Prior Art
Double-diffused MOS (DMOS) transistor devices have drawn much attention in power devices having high voltage capability. The conventional DMOS transistor devices are categorized into vertical double-diffused MOS (VDMOS) transistor device and lateral double-diffused MOS (LDMOS) transistor device. Having advantage of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other integrated circuit due to its planar structure, LDMOS transistor devices are prevalently used in high operation voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier. While sidewall spacers become thinner in the advance process nodes, leakage current (Ioff) of the DMOS will rise quickly because of the gate induced drain leakage (GIDL) effect and the heavier doped source/drain regions diffusing under the poly gate more seriously.